74AUP2G132

General description

The 74AUP2G132 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V_T+ and the negative voltage V_T- is defined as the input hysteresis voltage V_H.

Features

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• ESD protection:
  • HBM JESD22-A114E Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101C exceeds 1000 V
• Low static power consumption; I_CC = 0.9 uA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 pct of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Pricing/ordering/availability

Applications

• Wave and pulse shaper
• Astable multivibrator
• Monostable multivibrator

Block diagrams/pinning

Design support

Application Notes

AN10161_2; PicoGate Logic footprints (30-Oct-02)

Support Documents

75015252; Philips ultra-low-power CMOS logic 74AUP1G/2G/3Gxx (2005-11-01)

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