74HC137

General description

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.

The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH.

The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.

The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.

Features

• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active LOW mutually exclusive outputs
• Low-power dissipation
• Complies with JEDEC standard no. 7A
• ESD protection:
• HBM EIA/JESD22-A114-B exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from -40 Cel to +80 Cel and from -40 Cel to +125 Cel.

Products/packages

Pricing/ordering/availability

Design support

Support Documents

HCT_USER_GUIDE; HC/T User Guide (1997-11-01)

75013486; Philips Logic Competitive Cross Reference Guide (2004-09-14)

Parametrics/similar products

Similar products
74HC137 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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